I'm a Ph.D. student in Georgia Tech Electronical and Computer Engineering department. My advisor is Dr. Callie(Cong) Hao, and I am co-advised by Dr. Sung-kyu Lim.
My research interests focus on Monolithic 3DIC, Electronic Design Automation (EDA), 3D FPGA design, and Machine Learning. Recently I have been researching backside Power Delivery Networks (PDN), Heterogeneous Integration System Security, and building EDA tools for Field Programmable Analog Arrays (FPAA).
📧 Email address: [email protected]
🔗 LinkedIn: https://www.linkedin.com/in/hang-yang-857478218/
🏢 Office: Sharc lab, Klaus Advanced Computing Center, Room 2304
Ph.D. in Electrical and Computer Engineering (ECE),
Atlanta, GA August 2022 – Present, Expected Graduation, June 2027.
B.E. in Computer Science,
Tianjin, China September 2018 – July 2022.
INVITED: A Design Methodology for Back-side Power and Clock Routing Co-Optimization
IEEE Symposium on VLSI Technology & Circuits, 2024.
Analog System High-level Synthesis for Energy-Efficient Reconfigurable Computing
Journal of Low Power Electronics and Applications (JLPEA)
Rapid-INR: Storage Efficient CPU-free DNN Training Using Implicit Neural Representation
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023
Rapid-INR: Storage Efficient CPU-free DNN Training Using Implicit...
Unsupervised Learning for Combinatorial Optimization with Principled Objective Relaxation Neural Information Processing Systems (NeurIPS), 2022
Unsupervised Learning for Combinatorial Optimization with...