I'm a Ph.D. candidate in Georgia Tech Electronical and Computer Engineering department. My advisor is Dr. Callie(Cong) Hao, and I am co-advised by Dr. Sung-kyu Lim.
My research interests focus on AI/ML and EDA for 3D-IC, 3D-FPGA, and Computer Architecture. My projects include GNN-assisted EDA optimization, backside 3D-IC, and reconfigurable system. Recently I have been focusing on 3D-FPGA implementation and scalability challenges faced in ML for EDA.
📧 Email address: [email protected]
🔗 LinkedIn: https://www.linkedin.com/in/hang-yang-857478218/
🏢 Office: Sharc lab, Klaus Advanced Computing Center, Room 2304
Ph.D. in Electrical and Computer Engineering (ECE),
Atlanta, GA August 2022 – Present, Expected Graduation, June 2027.
B.E. in Computer Science,
Tianjin, China September 2018 – July 2022.
LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration
[⋆ Best Paper award] ACM/IEEE 44th ICCAD, 2025
Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI
IEEE MLCAD Symposium, 2025
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect
ACM Transactions on Design Automation of Electronic Systems, 2024
INVITED: A Design Methodology for Back-side Power and Clock Routing Co-Optimization
IEEE Symposium on VLSI Technology & Circuits, 2024.
Analog System High-level Synthesis for Energy-Efficient Reconfigurable Computing
Journal of Low Power Electronics and Applications (JLPEA)
Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing